module fft_core
#(
  parameter DATA_SIZE  = 32,
  parameter DFT_POINTS = 8
)(
  //OUTPUTS
  output [DATA_SIZE - 1:0] bus_rd,
  output bus_rdy,
  output interrupt,
  output busy_n,
  //INPUTS
  input [DATA_SIZE - 1:0] bus_wr,
  input [1:0] bus_addr,
  input read_en,
  input write_en,
  input enable,
  input clk,
  input rst_n
);

wire mem_src, mem_rd_core, mem_wr_core, start_butt;
wire addr_unit_en, config_src, config_en, int_set;
wire mem_rdy, butt_rdy, start;

fft_core_datapath 
#(
  .DATA_SIZE  ( DATA_SIZE  ),
  .DFT_POINTS ( DFT_POINTS )
)
  FFT_DATAPATH
(
  .bus_rd        ( bus_rd       ),
  .addr_unit_rdy ( addr_unit_rdy),
  .mem_rdy       ( mem_rdy      ),
  .bus_rdy       ( bus_rdy      ),
  .butt_rdy      ( butt_rdy     ),
  .interrupt     ( interrupt    ),
  .start         ( start        ),
  .bus_wr        ( bus_wr       ),
  .mem_src       ( mem_src      ),
  .busy_n        ( busy_n       ),
  .read_en       ( read_en      ),
  .write_en      ( write_en     ),
  .bus_addr      ( bus_addr     ),
  .mem_rd_core   ( mem_rd_core  ),
  .mem_wr_core   ( mem_wr_core  ),
  .addr_unit_en  ( addr_unit_en ),
  .start_set     ( start_set    ),
  .int_set       ( int_set      ),
  .config_en     ( config_en    ),
  .config_src    ( config_src   ),
  .start_butt    ( start_butt   ),
  .enable        ( enable       ),
  .clk           ( clk          ),
  .rst_n         ( rst_n        )
);

fft_core_control_unit FFT_CONTROL_UNIT
(
  .mem_src       ( mem_src),
  .mem_rd_core   ( mem_rd_core ),
  .mem_wr_core   ( mem_wr_core ),
  .start_butt    ( start_butt  ),
  .addr_unit_en  ( addr_unit_en),
  .config_src    ( config_src  ),
  .config_en     ( config_en   ),
  .int_set       ( int_set     ),
  .start_set     ( start_set   ),
  .addr_unit_rdy (addr_unit_rdy),
  .mem_rdy       ( mem_rdy     ),
  .butt_rdy      ( butt_rdy    ),
  .start         ( start       ),
  .busy_n        ( busy_n      ),
  .clk           ( clk         ),
  .rst_n         ( rst_n       )
);
endmodule
